In recently developed semiconductor technology, polysilicon material which has been used in transistor gates is also being used in interconnects. However, one drawback of the polysilicon material when used as a long distance conductor in a semiconductor device is its relatively high sheet resistance, i.e., at between 20 and 40 ohm/square in a doped form. The high sheet resistance can cause a significant delay in a polysilicon wire when used as a long distance conductor.
One solution to solve the high sheet resistance problem of doped polysilicon is to reduce the resistance by combining the polysilicon material with a refractory metal. It is a desirable approach since no extra mask work is required for the fabrication process. Silicides for such semiconductor applications can be formed by reacting a refractory or near noble metal with silicon. For instance, more commonly used silicides are titanium silicide (TiSi.sub.2), cobalt silicide (CoSi.sub.2), tungsten silicide (WSi.sub.2), platinum silicide (PtSi), molybedenum silicide (MoSi.sub.2), palladium silicide (Pd.sub.2 Si), and tantalum silicide (TaSi.sub.2). The most commonly used silicides are tungsten silicide, tantalum silicide and molybedenum silicide. These suicides are refractory metal suicides and therefore are thermally stable and resistant to processing chemicals. A silicide, such as tantalum silicide, can be used alone as a gate material presenting a sheet resistance of 1.about.5 ohm/square. Silicides can also be used in a sandwich form with polysilicon which is then known as a polycide, a condensed name for polysilicon-silicide. A polycide gate can achieve a low sheet resistance of less than 10 ohm/square which, represents a significant improvement from that of polysilicon alone.
When a polycide gate or a polycide line is used on a semiconductor device, a silicide layer is first blanket deposited over a layer of polysilicon and then the composite layers are patterned together. Based on its desirable low sheet resistance, the polycide structure can be advantageously used for local routing over short distances in the form of a polycide line. It is particularly desirable when only one or two levels of metals are used in a circuit as interconnects, since polycide lines can help to reduce the device size significantly.
When a polycide line is used in a multi-layer interconnect environment such as in a structure for a dynamic random access memory (DRAM), a dielectric material must be used in between the layers for insulation. For instance, to insulate a first metal layer from a silicon substrate, a dielectric material is typically deposited, planarized, and then patterned to define openings for contacts to silicon and polysilicon. This type of insulating dielectric material deposited is commonly referred to as a poly-metal dielectric (PMD) material. It can also be referred to as an inter-layer dielectric (ILD) material. An ideal PMD material should satisfy several property requirements. For instance, it should be contamination-free, it should exhibit a dielectric constant that approaches unity, and it should have a sufficiently high field strength and etch selectivity to underlaying materials such as suicides, silicon and polysilicon. It should also have gap filling capability in sub-half micron devices, it should also have good adhesion to the substrate and the overlaying metal, and it should also be a good barrier to ionic contaminants. It is also desirable that a PMD material can be easily planarized to facilitate subsequent fabrication steps.
More commonly used dielectric materials for PMD are boro-phophosilicate glass (BPS G), boro-phospho-tetra-ethoxy-silicate (BPTEOS) glass, phosphosilicate glass (PSG) and undoped silicate glass (USG). For instance, a typical PMD layer consists of a thick film (between about 3,000 .ANG. and about 15,000 .ANG.) of BPSG or BPTEOS which can be densified and reflowed at a temperature between about 700.about.900.degree. C., and preferably between about 750.about.850.degree. C. The reflow process of the PMD layer is important since a reflowed doped glass conformably covers steps and fills gaps between polycide lines and forms a nearly planar surface which is essential for subsequent fabrication steps. During a reflow (or planarization) process of a PMD layer in a semiconductor structure which has more than one PMD layers, problem occurs when the top PMD layer is heated to a temperature above its glass transition temperature in order to enable the material to flow.
Referring initially to FIG. 1A, where a semiconductor device 10 is shown. In the semiconductor device 10, a bird's beak field oxide isolation 12 is first formed in the surface layer of a silicon substrate 14. A PMD layer 16 of either BPSG or BPTEOS material is then deposited on top of the substrate and the field oxide isolation. After a polycide line 18 formed of a polysilicon layer 20 and a metal suicide layer 22 is deposited and patterned, a second PMD layer 26 is deposited of a material similar to that of the first PMD layer on top of the first PMD layer covering the polycide line. The surface 28 of the second PMD layer 26 is not planar and therefore must be planarized before the next fabrication step can be carried out.
The second PMD layer 26 can be reflowed at a reflow temperature that is higher than the glass transition temperature of the PMD material of either BPSG or BPTEOS, i.e., a suitable reflow temperature is in the range between 750.about.850.degree. C. After the reflow process, the top surface 30 of the second PMD layer 26 becomes substantially planar, however, at the expense of a deformed polycide line 18 which has moved away from its original position by the distance 32. This is shown in FIG. 1B.
The phenomenon of the deformation or movement of the polycide line 18 can be explained as follows. During the reflow process of the second PMD layer 26, the temperature of the device 10 must be raised to a temperature that is above the glass transition temperature of the dielectric material. Since the second PMD layer and the first PMD layer are usually deposited of a similar material, the reflow temperature required for the second PMD layer is also above the class transition temperature of the first PMD layer. As a consequence, both the first and the second PMD layers 16 and 26 soften and transform to a liquid state with the polycide line 18 suspended in the middle of two liquid layers. The polycide line 18 therefore deforms or drifts depending on the topography of the first PMD layer 16.
The deformation or drift of a polycide line after a reflow process can also be examined from FIGS. 2 and 3. FIG. 2 shows a polycide line 36 which has two polycide contacts 38 and 40. Prior to the reflow process, the polycide line 36 is in a straight line configuration as originally patterned in the fabrication step. After a reflow process is carried out at a temperature higher than the glass transition temperature of the two PMD layers between which the polycide line is sandwiched, the line bends drifts to the right at its middle point since there is no support by the underlaying first PMD layer. The polycide contacts 38 and 40 have not moved since they are anchored to polysilicon gate structures situated in the first PMD layer.
A similar deformation of another polycide line 46 is shown in FIG. 3. While the polycide contact 48 has not moved because it is anchored to a gate structure below, the polycide line 46 has drifted (or twisted) to the right since the lower part of the polycide line 46 is not anchored and therefore is free to move when the first and the second PMD layers transform into a liquid state during the reflow process. It should be noted that the deformation or drifting shown in FIGS. 2 and 3 are for illustration purpose only, and the true deformation or drifting depends on the topography of the PMD layer on which the polycide line is situated. The deformation or drifting of polycide lines presents a serious problem in the reliability of a semiconductor device since a polycide line may be drifted away from its original position and as a result, contacting other unintended via or interconnect and causing a short in the device. The deformation or drifting of a polycide line during a reflow process for the dielectric layers must therefore be controlled or avoided.
It is therefore an object of the present invention to provide a method for preventing a polycide line situated between two dielectric layers in a semiconductor device from deformation during a reflow process for the top dielectric layer.
It is another object of the present invention to provide a method for preventing a polycide line situated between two dielectric layers in a semiconductor device from deformation during a reflow process for the top dielectric layer that does not require significant modification of the fabrication process.
It is a further object of the present invention to provide a method for preventing a polycide line situated between two dielectric layers from deformation during a reflow process for the top dielectric layer that can be easily integrated into an existing fabrication process for the semiconductor device.
It is yet another object of the present invention to provide a method for preventing a polycide line situated between two dielectric layers from deformation during a reflow process for the top dielectric layer by hardening the polycide line through an annealing process such that the hardness of the line increases sufficiently to prevent deformation.
It is still another object of the present invention to provide a method for preventing a polycide line situated between two dielectric layers in a semiconductor device from deformation during a reflow process for the top dielectric layer by annealing the semiconductor device in a furnace at a sufficient temperature for a sufficient length of time such that the hardness of the line increases.
It is another further object of the present invention to provide a semiconductor structure that has at least one polycide line situated in between two dielectric layers that does not have the polycide line deformation problem during a reflow process for the top dielectric layer.